Saxo-smm: a Distributed Multiprocessor and a Balanced Architecture

In this paper, we show how a multiprocessor can be physically detached from its main memory using commercially available secondary cache controllers and high-speed ber optic links organized as a star network. The implementation connects up to eight Motorola 88110 processors to a single memory controller/directory cache. The memory access latency in this arrangement is lower. Communication time in the optical ber and protocol overhead do not substantially aaect the memory access time.